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TSMC and Taiwanese scientists have created a 2-D transistor on MoS₂ with an atomic buffer.

AuthorEditorial team 8-08-2026, 12:00 411
TSMC and Taiwanese scientists have created a 2-D transistor on MoS₂ with an atomic buffer.
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In brief
  • TSMC, together with Taiwanese scientists, has created a 2-D MoS₂ transistor.
  • An atomic buffer of Al₂O₃ allows for the deposition of HfO₂ without defects.
  • The equivalent oxide thickness reached ~1 nm with high mobility.
  • The technology is still in the demonstration phase, but it paves the way for scaling.

The reduction of silicon chip sizes is approaching physical limits, and the industry is increasingly seeking alternative semiconductor materials. Two-dimensional crystals, such as MoS₂, attract attention due to their thickness of one to two atomic layers (about 0.7 nm) and potentially better channel controllability at strong scaling.

However, the practical implementation of MoS₂ faces a serious obstacle – the inability to form a quality gate dielectric. The standard atomic layer deposition (ALD) method does not adhere well to the nearly non-chemical surface of the 2-D crystal, and the use of high-k materials, such as HfO₂, leads to electron scattering and a decrease in their mobility.

New technological approach

Researchers solved the problem by creating an atomically thin buffer layer between MoS₂ and the gate dielectric. In ultra-high vacuum, aluminum approximately 0.3 nm thick was deposited onto the surface of MoS₂ using electron beam evaporation. Due to the van der Waals nature of MoS₂, aluminum grew in the Al(111) orientation, after which it was controllably oxidized to obtain a uniform layer of Al₂O₃.

The resulting Al₂O₃ layer served as an ideal platform for subsequent ALD deposition of a high-k dielectric – HfO₂. The buffer simultaneously provided a smooth surface for HfO₂ growth and isolated the MoS₂ channel from undesirable interactions with this material.

As a result, the obtained short-channel transistors managed to reduce the equivalent gate thickness to approximately 1 nm without degrading carrier mobility. This combination led to a high subthreshold swing, which is a key parameter for energy-efficient logic elements.

Monolayer MoS₂, being only 0.7 nm thick, demonstrates better resistance to short-channel effects compared to silicon, making it an attractive candidate for further size reduction of logic nodes.

Currently, the work represents a technological principle rather than a ready replacement for silicon CMOS. However, it confirms that the main barrier of two-dimensional electronics – creating an ultra-thin gate without degrading the atomic channel – can be overcome through an atomic buffer interface, which is already becoming an integral part of future transistors.

Source: 3DNews

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